1. Field of the Invention
The present invention relates to a manufacturing method of a semiconductor device and more particularly of a cylindrical stacked electrode.
2. Description of the Related Art
In a DRAM (Dynamic Random Access Memory) whose respective memory cells are constituted from one transistor and one capacitor, a higher degree of integration has been generally achieved by the miniaturization of memory cells. Accompanying the reduction of the memory cell area, however, an area that one capacitor can occupy has decreased such an extent that it has become difficult to provide the sufficient amount of storage charge Cs (25fF) to maintain a resistance against soft errors. At present, a storage electrode called the layered type (stacked type) is widely used in general, and a technique to enlarge the practical area of this electrode by forming, on the surface of the storage electrode, minute hemispherical crystalline grains of silicon, that is HSG-Si (Hemispherical Grained-Si), has come into use. Further, in addition to this HSG formation technique, another technique that uses a stacked capacitor having a three-dimensional cylindrical structure has been being applied in order to cope with high integration. Nevertheless, at the level of a 256M DRAM, an amount of storage charge Cs that can be obtained in a simple cylindrical capacitor or an HSG stacked capacitor is as little as 18 fF on calculation. Therefore, as the integration proceeds further from a 256M DRAM, it becomes necessary to use either a high dielectric layer such as Ta.sub.2 O.sub.3 in place of Si.sub.3 N.sub.4, or alternatively a capacitor structure combining a cylindrical type and an HSG type. The high dielectric layer is likely to be utilized in the future, but, in the present stage, is still on the way to development and difficult to put into practical use in semiconductor devices. Accordingly, a combined structure of a cylindrical type and an HSG type, each of which is proven to work, is the most promising as a stacked capacitor structure for a 256 M DRAM.
Furthermore, in the case of a simple cylindrical stacked electrode, a sidewall section in the forthcoming high integration semiconductor device will become very thin and the space between electrodes will become very narrow. Accordingly, there will arise a problem of its collapse during a wet step such as a cleaning after the formation of the cylindrical stacked electrode is completed. In the case that the HSG formation technique is applied to the conventional cylindrical stacked electrode, however, the sidewall section becomes even thinner and the problem of the sidewall collapse becomes more serious, since the HSG formation technique utilizes the silicon migration on the surface of a silicon layer. Therefore, how to heighten the mechanical strength of the sidewall section during the formation of the electrode becomes a crucial point.
Now, problems in manufacturing methods of conventional cylindrical stacked electrodes are described in detail. Referring to FIG. 2a to FIG. 2f, which are cross sectional views illustrating, in sequence, steps of the manufacturing method of a semiconductor device, a first conventional art is described.
First, a field oxide film 202 is formed in an isolation region on the surface of a P-type silicon substrate 201, and a gate oxide film 203 is formed in the other region that is uncovered with the field oxide film on the silicon substrate. After a gate electrode 204 which also functions as a word line is formed on both the gate oxide film 203 and the field oxide film 202, N-type diffusion layers 205 and 206 which are to become source-drain regions are formed by the ion implantation method or the like. Next, an insulating film 207 of silicon oxide is deposited by the CVD (Chemical vapor Deposition) method and then a bit line 208 is formed. An interlayer insulating film 207a is deposited thereon, and thereafter, using a photoresist (not shown) as a mask, a contact hole 209 is made to expose a portion of the N-type diffusion layer 205 (FIG. 2a).
Next, a phosphorus-doped silicon film 210 is grown to a thickness of 150 nm or so, burying the contact hole 209. Further, a silicon oxide film NSG (Non-doped Silicate Glass) 211 is grown to a thickness of 700 nm or so, and thereafter, using a photoresist (not shown) as a mask, a hole 212 is made (FIG. 2b).
Next, a phosphorus-doped silicon film 213 is grown to a thickness of 100 nm or so, and then, using a photoresist 214, the hole 212 is buried in such a way that a gap section where a sidewall section of a cylindrical stacked electrode is to be formed is left open. Following this, a phosphorus-doped silicon film 213 is grown again and then, performing the dry etching-back, the phosphorus-doped silicon film 213 is exposed, as shown in FIG. 2c.
Next, the phosphorus-doped silicon film 213 is etched back by means of dry etching and the silicon oxide film NSG 211 is exposed. After this, the silicon oxide film 211 is removed with a HF (Hydrofluoric Acid) solution (FIG. 2d).
Next, a portion of the phosphorus-doped silicon film 210 that is all but an area directly below a cylindrical stacked electrode 215, is removed by means of dry etching-back, and finally the photoresist 214 is removed with SPM (Sulfuric acid-Hydrogen peroxide Mixture) solution, and thereby a cylindrical stacked electrode 215 is accomplished (FIG. 2e).
Further, referring to FIG. 3a to FIG. 3e, which are cross-sectional views illustrating, in sequence, steps of the manufacturing methods of a semiconductor device, a second conventional art is described. The reference numerals 301 to 308 in the drawings correspond to the numerals 201 to 208 in FIG. 2 shown above and a further description hereat is left out.
An interlayer insulating film 307a is deposited and then a contact hole is made, as described above, and thereafter a silicon film 309 is grown to a thickness of 1 .mu.m or so. At this, the silicon film 309 has a layered structure in which a phosphorus-doped silicon film 309a with a thickness of 150 nm is first formed and thereon an O.sub.2 leakage layer is stacked, and, further, another phosphorus-doped silicon film 309b with a thickness of 490 nm and thereon a second O.sub.2 leakage layer and, further over those, a non-doped silicon film 309c with a thickness of 430 nm are stacked, in succession. The silicon films 309a to 309c are characterized by being successively grown in a furnace (FIG. 3a).
Next, using a photoresist (not shown) as a mask, the non-doped silicon film 309c within the layered phosphorus-doped silicon film 309 alone is etched. The O.sub.2 leakage layer serves as a stopper layer for this etching. Further, after a silicon oxide film 310 is grown to a thickness of 250 nm or so, dry etch-back is carried out so as to leave a portion of the silicon oxide film 310 by the sidewall section of the non-doped silicon film 309c (FIG. 3b) Next, using the silicon oxide film 310 as a mask, the phosphorus-doped silicon film 309 is subjected to the dry etching. In this instance, with the O.sub.2 leakage layer serving as a stopper layer, the bottom section of a cylindrical stacked electrode is prevented from reaching the interlayer insulating film (FIG. 3c). Next, the silicon oxide film 310 is removed with a HF solution, and thereby the formation of a cylindrical stacked electrode 311 is accomplished (FIG. 3d).
When the HSG formation technique is applied to the cylindrical stacked electrodes 215 and 311 which are manufactured according to the two conventional methods described above, HSG cylindrical combination-type stacked electrodes 216 and 312 are produced, respectively. Those electrodes each have their own shortcomings. First, in the electrode manufactured by the second conventional art, the formation of HSG-Si can be effected only in the upper section of the electrode, as shown in FIG. 3e. This results from a fact that the growth rate of phosphorus-doped silicon films is as low as several nm/min and, during a growth time thereof, which is consequently long, a gradual crystallization of silicon takes place. Moreover, the long growth time is a problem itself in respect of the manufacturing efficiency. Further, because the stopper used at the time of dry etching is the O.sub.2 leakage layer and etch rates somewhat vary, the reproductivity of the electrode comes into question. Another problem is a possibility that an interlayer insulating film 307a is etched, in removing the silicon oxide film 310 used as the final mask.
Concerning the first conventional art, it is necessary to grow the phosphorus-doped silicon film 210, at least, to a thickness of 150 nm or so, in order to bury the contact hole 209 completely. Therefore, when this film 210 is finally removed by means of dry etch-back, the sidewall section of the electrode is made thin, due to a substantially long time taken to perform the dry etch-back, which lowers the mechanical strength of the electrode. Further, while the photoresist is utilized to protect the bottom section of the cylindrical electrode, in addition to the silicon film 210 formed in burying the first contact hole 209, another silicon film 213 is also formed as a film in the bottom section at the time of the sidewall section formation so that the films at the bottom of the electrode become thick. This causes another problem that a capacitance obtainable inside of the stacked capacitor in this art is relatively small for its height.